With the increase in internet traffic and demand for high-bandwidth applications such as high-performance computing, data-center connectivity and video content distribution, total aggregate bit rate in integrated circuits (ICs) is increasing both in line rate and number of parallel channels. This drives the need to test ICs at maximum operating rate in order to guarantee high yield in the product. Current Automatic Test Equipment (ATE) is not capable for this type of test both in bandwidth and in number of channels. Without the capability of full-speed test at the ATE level, one will either have to take a yield loss in final assembly, or to attach high-speed add-ons to the ATE or to introduce a second insertion on a test platform that has the full-speed capability. All of the aforementioned solutions add costs to the IC and/or the product in which it is used. Hence there is a need for a low-cost, full-speed self-test.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.